1. Field of the Invention
The present invention relates to a solid-state image pickup device constituted by semiconductor elements, and particularly to an X-Y address type solid-state image pickup device manufactured by a CMOS process.
2. Description of the Related Art
In recent years, solid-state image pickup devices are incorporated in various products, such as digital still cameras, digital video cameras, or portable telephones, and are used in large quantities. The solid-state image pickup device is roughly classified into a CCD (Charge Coupled Device) solid-state image pickup device constituted by a charge transfer image sensor, and an X-Y address type solid-state image pickup device in which an image sensor is constituted by, for example, CMOS (Complementary Metal Oxide Semiconductor) transistors. The X-Y address type solid-state image pickup device using a CMOS image sensor (hereinafter suitably abbreviated to a CMOS image sensor) can be manufactured by the same technique as a manufacturing process of a MOSFET, and it is driven by a single power source and consumed electric power is also low, and further, various signal processing circuits can be mounted on the same chip. Thus, the CMOS image sensor is regarded as promising in substitution for the CCD solid-state image pickup device.
A conventional X-Y address type solid-state image pickup device using this CMOS image sensor will be described with reference to FIG. 6. FIG. 6 shows a circuit example of one pixel of the conventional X-Y address type image sensor. The conventional CMOS image sensor shown in FIG. 6 has, for example, an APS (Active Pixel Sensor) structure in which a source follower amplifier 404 is mounted in each pixel. A cathode side of a photodiode 400 is connected to a gate electrode of the source follower amplifier 404 and a MOS type reset transistor 402. Besides, the source follower amplifier 404 is connected to a vertical selection line 408 through a horizontal selection transistor 406.
The operation of this conventional CMOS image sensor will be described in brief. First, a reset signal RST is applied to a gate electrode of the reset transistor 402 at a predetermined timing so that the reset transistor 402 is turned on. By this, the photodiode 400 is charged to a reset potential VR. Next, with the incidence of light, the photodiode 400 starts to discharge and the potential is lowered from the reset potential VR. An incident photon during an integration period is subjected to photoelectric conversion to generate a pair of an electron and a hole. The electron is stored in the photodiode in a floating state, and the hole is absorbed by a semiconductor substrate biased to the ground. When a signal electric charge is Qsig, a potential change ΔVPD of the photodiode 400 by a signal electron is given by ΔVPD=Qsig/Cs. When a horizontal selection signal RWn is inputted to a gate electrode of the horizontal selection transistor 406 after a predetermined time has elapsed and the horizontal selection transistor 406 is turned on, a voltage of the source follower amplifier 404 is extracted as a signal voltage through the vertical selection line 408.
However, in the conventional APS structure in which the charge storage capacitance photodiode 400 and the source follower amplifier 404 are mounted, there is a problem that a fixed pattern noise (FPN) in which a DC level of a signal voltage is changed by fluctuation of a threshold voltage VT or the like, is generated and picture quality is deteriorated. In order to reduce this, a correlated double sampling (CDS) circuit is used. First, after a signal voltage is sampled by the correlated double sampling circuit, the photodiode 400 is reset to the reset potential VR. Next, the reset voltage is sampled by the correlated double sampling circuit, and a difference between the signal voltage and the reset voltage is obtained. By this, the influence of the fluctuation of the threshold voltage VT is compensated and the FPN can be reduced.
However, in this method, since the reset voltage after signal storage, not the reset voltage before the signal storage (integration), is sampled to obtain the difference between the reset voltage and the signal voltage, there is no correlation between a kTC noise (thermal noise) superimposed on the signal voltage and a kTC noise superimposed on the sampled reset voltage. Thus, there remains a problem that the kTC noise generated at random from the photodiode 400 in a reset period can not be removed by the CDS circuit, and the S/N ratio is deteriorated as compared with the CCD solid-state image pickup device.
The kTC noise is generated when the reset transistor 402 is brought into an on state and the photodiode 400 is reset to the initial potential, and is a random noise expressed by νkTC=(kT/C)½. Where, k is the Boltzman constant, T is absolute temperature, and C is total capacitance stored in the photodiode 400.
Next, a CMOS image sensor capable of reducing the kTC noise will be described with reference to FIG. 7. In FIG. 7, a transfer gate FT for forming an energy barrier is provided between a first capacitance C1 of a photodiode 400 and a second capacitance C2 of a floating diffusion (FD) region, and a source follower amplifier 404 is connected between the transfer gate FT and a horizontal selection transistor 406 constituted by a MOSFET. A MOS type reset transistor 402 for removing an electric charge stored in the second capacitance C2 is connected to the second capacitance C2. A drain electrode of the source follower amplifier 404 is connected to a power source VDD, and its source electrode is connected to the horizontal selection transistor 406. A gate electrode of the source follower amplifier 404 is connected to the second capacitance C2. A reset potential VR is applied to a drain electrode of the reset transistor 402. A source electrode of the reset transistor 402 is connected to the second capacitance C2, and a reset signal RST is inputted to its gate electrode.
When an electric charge is transferred to the second capacitance C2 of the FD region by turning on the transfer gate FT after the electric charge is stored in the first capacitance C1, the potential of the gate of the source follower amplifier 404 becomes gradually high. When the horizontal selection transistor 406 is turned on after a predetermined time has elapsed, the source voltage of the source follower amplifier 404 is outputted through a vertical selection line 408, and an electric charge quantity Q stored in the second capacitance C2 can be detected. When the reset transistor 402 is turned on only once before the transfer gate FT is turned on, all electric charge stored in the second capacitance C2 can be removed, and deterioration of picture quality due to a residual electric charge can be suppressed.
According to this structure, since the signal voltage after resetting can be sampled after the reset voltage prior to the signal storage is sampled, the kTC noises respectively superimposed on the reset voltage and the signal voltage have high correlation. Thus, when the signal voltage is sampled after the reset voltage is sampled and the difference between the reset voltage and the signal voltage is obtained by using the correlation double sampling circuit, the kTC noise of the signal voltage can be reduced.
However, in the structure of the conventional CMOS image sensor shown in FIG. 7, as described above, although the FPN and the kTC noise can be reduced, there is a problem that the element structure becomes complicated. The element structure of the pixel shown in FIG. 7 has a problem that as compared with the element structure of the pixel shown in FIG. 6, the number of the transistors is increased, the pixel portion becomes complicated, and the opening ratio (fill factor) of a light receiving portion is lowered.
Next, another example of a CMOS image sensor capable of reducing the kTC noise will be described with reference to FIG. 8. The CMOS image sensor shown in FIG. 8 includes a control circuit for controlling a reset voltage applied to a gate electrode of a reset transistor 402 to reduce the kTC noise, in addition to the element structure shown in FIG. 6.
A reference reset signal VR is inputted to a non-inverting input terminal of an operational amplifier 412 of the control circuit. A signal at a connection point between a cathode terminal of the photodiode 400 and the reset transistor 402 is inputted through a wiring line 416 to an inverting input terminal of the operational amplifier 412. The wiring line 416 is arranged in a pixel region. Besides, a constant current source 414 is connected to the inverting input terminal of the operational amplifier 412. An output terminal of the operational amplifier 412 is connected to the gate electrode of the reset transistor 402 through a switch circuit 410.
In the control circuit of such structure, when a signal Vg is inputted to a gate electrode of the switch circuit 410 at a predetermined reset timing and the switch circuit 410 is turned on, a gate voltage of the reset transistor 402 is controlled so that a potential at the cathode side of the photodiode 400 always becomes the reset voltage VR. By doing so, the kTC noises respectively superimposed on the signal voltage and the subsequent reset signal after signal storage can be made to have an almost constant level. Thus, when the reset signal after the signal storage is sampled and a difference between the sampled voltage and the signal voltage is obtained by a CDS circuit, the kTC noise can be reduced. However, in this structure, since it becomes necessary to arrange the wiring line 416 in the pixel region, there arises a problem that an opening ratio is not made wide.
As described above, the CMOS image sensor shown in FIG. 6 has the problem that the kTC noise can not be reduced. On the other hand, the CMOS image sensors shown in FIGS. 7 and 8 have the problem that in exchange for reduction of the kTC noise, the element size becomes large and a wide opening ratio can not be obtained.